Implementation notes: riscv64, riscvunleashed000, crypto_hash/lane512

Computer: riscvunleashed000
Microarchitecture: riscv64; U54 (sifive,u54-mc)
Architecture: riscv64
CPU ID: unknown CPU ID
SUPERCOP version: 20240107
Operation: crypto_hash
Primitive: lane512

Time	Object size	Test size	Implementation	Compiler	Benchmark date	SUPERCOP version
495206	90628 0 0	99201 776 728	`T:c`	`clang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240113	20231222
495301	90628 0 0	98781 776 728	`T:c`	`clang_-march=rv64imafdc_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240113	20231222
495381	90458 0 0	96957 768 721	`T:c`	`clang_-march=rv64imafdc_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240113	20231222
495523	90628 0 0	99201 776 728	`T:c`	`clang_-march=rv64imafdc_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240113	20231222
495686	90628 0 0	98781 776 728	`T:c`	`clang_-march=rv64imafdc_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240113	20231222

Compiler output

Implementation: T:c
Security model: timingleaks
Compiler: gcc -mcpu=sifive-u54 -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE

lane.c: Alarm clock

Number of similar (compiler,implementation) pairs: 4, namely:

Compiler	Implementations
gcc -mcpu=sifive-u54 -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	T:c
gcc -mcpu=sifive-u54 -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	T:c
gcc -mcpu=sifive-u54 -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	T:c
gcc -mcpu=sifive-u54 -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	T:c